DFSX claims an HBM-free AI chip with double NVIDIA's system bandwidth on 14nm
Dongfang Suanxin, known as DFSX, stacks DRAM directly on top of the compute die using 3D wafer-level hybrid bonding. That fuses the copper paths of both layers and removes microbumps entirely. The reason the design exists: it needs no HBM at all, and high bandwidth memory is exactly what export controls have made hardest for Chinese firms to obtain.
The claim
A TY64 SuperNode built from 14nm DF2000 chips delivers 960 TB/s of memory bandwidth, against 576 TB/s for NVIDIA’s GB200 NVL72 system. The already-shipping DF1000 is rated at 6.4 TB/s per chip with 900 GB/s of scale-up bandwidth for chip-to-chip traffic. DF2000 is expected in the fourth quarter of 2026.
Handle with care
Those numbers come from DFSX itself. No independent lab has benchmarked a TY64, and 14nm sits several generations behind the 4nm-class process NVIDIA uses. Bandwidth is also one axis out of many: compute density, yield, power draw and software maturity all decide whether a system is usable at scale.
Why it matters anyway
The strategic idea is the interesting part regardless of whether the specific numbers hold. If you cannot buy the best process node or the best memory, you change where the memory sits. Whether architecture is a real way around export controls, or the process gap wins in the end, is now a live experiment running at national scale.
Sources
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